Encore Concept 32/67 Computer

INTRODUCTION

Encore manufactured a series of 32 bit minicomputers, computers with the same orthogonal instruction set, but with different performance parameters. The following models were manufactured; 32/27, 32/67, 32/77, 32/87 and 32/97. The 32/27 was the slowest model, whereas the 32/97 was an ECL implementation of the SEL architecture and was the fastest of the family. The 32/77 system I managed at Concordia University (Montreal) was implemented on three wire wrapped boards using TTL LSI circuits. It also featured Writable Control Store (WCS), giving the ability to create custom microcoded instructions. One student created an Euclid interpreter in WCS as part of his Master's thesis.

This section describes the 32/67 as an example.

MULTISel offered a system-level solution for tightly-coupled, distributed processing by providing up to four CPU/IPU nodes in a single, compact cabinet. Up to nine nodes could function as a single multi- processing system with one node designated as the system host.

MULTISel enabled the user to apply the right amount of processing power to individual application areas by assigning them to independent, but closely coupled, MULTISel nodes. Gould’s unique Reflective Memory system linked these nodes to provide each with a common address range for data needed by all nodes in the system.

MULTISel configurations with various hosts allowed hardware and software support for up to nine nodes forming a single system. The controlling host node could be a CONCEPT 32/97, 32/87. SELPAC or another MULTISel, depending on application requirements. With a CONCEPT 32/97 or 32/87. The image on the right is that of a 32/87 or 32/97 system, which used a wider cabinet than the 32/67.

The MULTISel Host/Node Peripheral Cabinet differed from the standard node cabinet in that it was designed to accommodate peripheral devices in the upper half. Each node supported standard CONCEPT/32 hardware and software and ran its own copy of the MPX-32 Operating System, which was downloaded from the host node. Nodes were available in eight and 16 SelBUS slot versions.

An optional MULTISel MPX-32-based package consisting of six application tasks provided the necessary tools to configure, download, control and monitor up to eight nodes from a single host.

MULTISel Configuration

1. A vertically cooled 8 or 16 slot Se1BUS chassis
2. Power sequencing module
3. CMOS CPU
4. Floating Point Co-processor/Accelerator (FPA)
5. Multi-Function Processor (MFP)
6. 2MB or 8MB Dual-Port Integrated Memory Module (DPIMM)
7. Reflective Memory port

Each of these components is implemented on a single circuit board. MULTISel nodes could also have an Internal Processing Unit (IPU) which is a secondary computational processor. It can also have its own FPA.

32/67 CENTRAL PROCESSING UNIT

The single-board CMOS CPU was implemented in VLSI gate array technology. The Floating point co-processor (FPA) used surface mount chips and FAST-logic technology to produce a single-board, floating-point accelerator that was used as a co-processor with the CPU and IPU. The FPA performed floating point arithmetic operations and fixed-point multiplication in a fraction of the time performed by firmware alone. Both 32-bit single precision and 64-bit double precision operands are supported.

This balanced architecture allows the programmer to segment applications and specify which tasks are to be given to the CPU or IPU. Instructions not allowed in the IPU are passed to the CPU for execution. Although the IPU is transparent to most users, some multitasking applications can be affected by the concurrent execution of individual tasks. For example, two tasks which access a shared database may need to use MPX-32 synchronization primitives to avoid inconsistencies in the database. Tasks may also specify that they need to run in the CPU for all or part of their execution.

The CPU is a 32-bit system, with a logical and physical address space of 16MBytes. It featured 8 general purpose registers. The CPU implements 214 instructions including floating point instructions in firmware (optional hardware FPA is available). Memory protection, power fail-safe, ECC memory and arithmetic exception traps were among the CPU's integrity features.

The CPU cache was two-way set associative with a size of 32KBytes; 16KBytes for operands and 16KBytes for data. Performance was rated at 2.6 MIPs.

MEMORY

Dual-Port Integrated Memory Modules (DPIMMs) provided 2MBytes or 8MBytes of memory. DPIMMs featured two-way, on-board interleaving, which alleviated memory contention problems and improved memory access in various applications. The second port of the DPIMM supported Reflective Memory DPIMMs and can provide 16MB of memory using only two slots. The memory cycle time was 150ns with a width of 39 bits; 32 bits for data and 7 bits for ECC. Memory interleaving was 2-way as a standard but could optionally be 4-way. The CPU could address 16MBytes of memory.

Reflective Memory

With Reflective Memory, Nodes retain their own private memory while taking advantage of a common, logically linked reflective memory partition. This partition contains data required by all nodes in the system, in effect providing each with its own copy of the data base. Any node writing to this partition causes that write to be immediately transferred to other nodes reflective memory partitions. Thus, each node has free access to its own constantly updated copy of the application data.

Reflective Memory Operation

Reflective Memory relies on the following components:

• DPIMMs
• Reflective Memory Port: Read Sense Controller (RSC), Write Sense Controller (WSC) device interface card sets, Reflective Memory Bus (RMB)

The RSC monitors the RMB and the WSC monitors the SelBUS for addresses soft-programmed to specify the reflective portion of memory. The RSC and WSC contain buffers for queuing requests to or from the RMB, which eliminates additional processing time. The RMB is a high-speed bus that transfers data at the SELBUS rate of 26.67 MBytes per second.

INTERRUPTS AND TRAPS

Encore computers can accommodate up to 112 hardware priority interrupt levels used for I/O Controllers, integrity features, and external signals. The interrupts associated with the I/O are provided by the I/O Controllers. The Real-Time Option Module (RTOM) provides 18 external interrupt levels, a real-time clock, and a 32-bit programmable interval timer. The real-time clock and interval timer each uses one interrupt level.

Each interrupt level has an assigned dedicated memory location. All interrupt levels, except power fail/restart and system override, can be selectively enabled, disabled, activated, deactivated, or requested under software control. All Interrupt Control Instructions are privileged. Attempts at execution by unprivileged programs will cause a Privilege Violation Trap.

One RTOM is included in all configurations. Only two of the basic integrity features and four MPX-32 interrupts require interrupt levels on the first RTOM. These are Power Fail/Auto Start, System Override, Console Interrupt, CALM, Real-Time Clock, and Interval Timer. The other integrity features me implemented using traps. Ten external interrupts are available to the user.

I/O SYSTEM

SELBus

The SelBUS is a high-speed, synchronous, time division multiplexed bus that can transfer data at the rate of 26.67 million bytes per second. Interrupt and SelBUS priority are uniquely defined and are not module-position dependent. Each module is assigned 1 of the 23 SelBUS priority lines by simple jumper settings.

The SelBUS is a bi-directional bus. Thirty two data lines and twenty four address lines on the SelBUS are used to send and receive data between system components. These transfers can occur every 150 nanoseconds. The address lines are used to select the desired subsystem component or memory location for a data transfer operation. Both data and address lines operate simultaneously.

Multi-Function Processor (MFP)

Several SelBUS and Multipurpose Bus boards are consolidated on the Multi-Function Processor board. This board encompasses the following functions:

1. Console port Seven asynchronous ports
2. Line printer port
3. Real-time clock and interval timer
4. Twelve external interrupts
5. Two Small Computer Systems Interface (SCSI) buses. One dedicated to a fixed disk drive the other to a magnetic tape drive

MPX-32 PROGRAMMING LANGUAGES

MPX is a multitasking operating system that supports real-time, multi-batch and interactive processing applications.

Languages that are supported under MPX-32 include FORTRAN 86+, FORTRAN 77+, Pascal, COBOL, BASIC and Assembly Language. Libraries are pre-written subroutines that perform commonly used functions in the scientific, graphic and database applications areas. Tools help to expedite the creation of quality software by automating key processes within the development cycle.

Sources:

• Adapted from: Encore Support Site
• Adapted from: Multiprocessor system with reflective memory Patent

Compiled on 08-17-2023 14:48:17